AK8181C Datasheet, PDF (4/8 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:2 Clock Fanout Buffer

AK8181C
DC Characteristics
All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted
Parameter
Symbol
Conditions
Input High Voltage
VIH
Input
CLK0, CLK1
Low Voltage _{CLK_EN, CLK_SEL}
VIL
Input
CLK0, CLK1, CLK_SEL
High Current _{CLK_EN}
IH
CLK0, CLK1, CLK_SEL
Input
Low Current
IL
CLK_EN
Output High Voltage⁽¹⁾
VOH
Output Low Voltage⁽¹⁾
VOL
Peak-to-Peak Output
Voltage Swing
VSWING
Supply Current
IDD
(1) Outputs terminated with 50Ω to VDD-2V.
Vin=VDD=3.465V
Vin=VDD=3.465V
Vin=VSS,
VDD=3.465V
Vin=VSS,
VDD=3.465V
MIN
TYP
MAX Unit
2.0
VDD+0.3 V
-0.3
1.3
V
-0.3
0.8
V
150 μA
5
μA
-5
μA
-150
VDD-1.4
VDD-2.0
0.6
μA
VDD-0.9 V
VDD-1.7 V
1.0
V
50
mA
AC Characteristics
All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP MAX Unit
Output Frequency
fOUT
Propagation Delay⁽¹⁾
tPD
266 MHz
0.6
1.4
ns
Output Skew⁽²⁾⁽³⁾
tsk(O)
20
ps
Part-to-Part Skew⁽³⁾⁽⁵⁾
tskPP
200 ps
Buffer Additive Jitter, RMS tjit
Output Rise/Fall Time⁽⁴⁾ tr, tf
12kHz to 20MHz@156.25MHz
20% to 80%
0.03
ps
200
600 ps
Output Duty Cycle
DCOUT
48
50
52
%
(1) Measured from the VDD/2 of the input to the differential output crossing point.
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions.
(3) This parameter is defined in accordance with JEDEC Standard 65.
(4) Design value.
(5) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Feb-2013
draft-E-01
-4-