AK8181C Datasheet, PDF (2/8 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:2 Clock Fanout Buffer

AK8181C
Pin Descriptions
Package: 14-Pin TSSOP(Top View)
Pin No. Pin Name
1
VSS
Pin
Type
PWR
2
CLK_EN IN
3
CLK_SEL IN
4
CLK0
IN
5
VSS
PWR
6
CLK1
IN
7
8
9,10
11
12, 13
14
VDD
VDD
Q1n, Q1
NC
Q0n, Q0
VDD
PWR
PWR
OUT
---
OUT
PWR
Pullup
down
---
Pull up
Pull down
Pull down
---
Pill down
---
---
---
---
---
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Description
Negative power supply
Synchronizing clock output enable (LVCMOS/LVTTL)
Pin is connected to VDD by internal resistor. (typ. 51kΩ)
High (Open): clock outputs follow clock input.
Low: Q outputs are forced low, Qn outputs are forced high.
CLK Select Input (LVCMOS/LVTTL)
Pin is connected to VSS by internal resistor. (typ. 51kΩ)
High: selects CLK1 input Low (Open): selects CLK0 input
LVCMOS/LVTTL Clock Input
Pin is connected to VSS by internal resistor. (typ. 51kΩ)
*When using CLK1 input (CLK_SEL=High),it should be connected
to VSS or opened.
Negative power supply
LVCMOS/LVTTL Clock Input
Pin is connected to VSS by internal resistor. (typ. 51kΩ)
*When using CLK0 input (CLK_SEL=Low), it should be connected
to VSS or opened.
Positive power supply
Positive power supply
Differential clock output (LVPECL)
No connect
Differential clock output (LVPECL)
Positive power supply
PWR: Power pin, IN: Input pin, OUT: Output pin
Feb-2013
draft-E-01
-2-