AK4384_06 Datasheet, PDF (6/24 Pages) Asahi Kasei Microsystems – 106dB 192kHz 24-Bit 2ch ΔΣ DAC

ASAHI KASEI
[AK4384]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.5 ∼ 5.5V)
Parameter
Symbol
min
typ
Master Clock Frequency
Duty Cycle
fCLK
dCLK
2.048
40
11.2896
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
60
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
Audio Interface Timing
BICK Period
Normal Speed Mode
Double/Quad Speed Mode
tBCK
tBCK
1/128fs
1/64fs
BICK Pulse Width Low
tBCKL
30
Pulse Width High
tBCKH
30
BICK rising to LRCK Edge (Note 13) tBLR
20
LRCK Edge to BICK rising (Note 13) tLRB
20
SDTI Hold Time
tSDH
20
SDTI Setup Time
tSDS
20
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
CDTI Setup Time
tCCKH
80
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSW
150
tCSS
50
tCSH
50
Reset Timing
PDN Pulse Width
(Note 14) tPD
150
Notes: 13. BICK rising edge must not occur at the same time as LRCK edge.
14. The AK4384 can be reset by bringing PDN= “L”.
max
36.864
60
48
96
192
55
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS0176-E-01
-6-
2006/01