AK4384_06 Datasheet, PDF (19/24 Pages) Asahi Kasei Microsystems – 106dB 192kHz 24-Bit 2ch ΔΣ DAC

ASAHI KASEI
[AK4384]
SYSTEM DESIGN
Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4384) is available in order to allow an
easy study on the layout of a surrounding circuit.
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Mode
Setting
Digital Ground
1 MCLK
DZFL 16
2 BICK
DZFR 15
3 SDTI
VDD 14
4 LRCK
5 PDN
AK4384
VSS 13
VCOM 12
6 SMUTE
AOUTL 11
7 ACKS
AOUTR 10
8 DIF0
P/S 9
0.1u ⁺ 10u
10u
+
Analog Ground
Analog
Supply 5V
Lch
MUTE
Rch
MUTE
Lch Out
Rch Out
Figure 9. Typical Connection Diagram (Parallel Mode)
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Micro-
controller
Digital Ground
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 PDN
6 CSN
7 CCLK
8 CDTI
DZFL 16
DZFR 15
VDD 14
AK4384
VSS 13
VCOM 12
AOUTL 11
AOUTR 10
P/S 9
0.1u ⁺ 10u
10u
+
Analog Ground
Analog
Supply 5V
Lch
MUTE
Rch
MUTE
Lch Out
Rch Out
Figure 10. Typical Connection Diagram (Serial Mode)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-up pin should not be left floating.
MS0176-E-01
- 19 -
2006/01