AK4104_10 Datasheet, PDF (6/21 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 3.3V DIT

SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V, C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Frequency
Frequency
fCLK
2.048
Duty Cycle
dCLK
40
LRCK Frequency
Frequency
fs
8
Duty Cycle
dCLK
45
Audio Interface Timing
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
30
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
tBCKH
30
(Note 5) tBLR
20
(Note 5) tLRB
20
SDTI Hold Time
tSDH
20
SDTI Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tSDS
20
tCCK
200
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSS
150
tCSH
50
tDCD
tCCZ
Power-Down & Reset Timing
PDN Pulse Width
(Note 6) tPD
150
Note 5. BICK rising edge must not occur at the same time as LRCK edge.
Note 6. The AK4104 can be reset by bringing PDN pin = “L”.
[AK4104]
max
36.864
60
192
55
45
70
Units
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS0642-E-01
-6-
2010/09