AK4104_10 Datasheet, PDF (10/21 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 3.3V DIT

[AK4104]
OPERATION OVERVIEW
■ Reset and Initialization
The AK4104 should be reset once by bringing PDN = “L” upon power-up. It takes 8 bit clock cycles for the AK4104 to
initialize after PDN pin goes “H”.
■ MCLK and LRCK Relationship
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through a
frequency divider) or indirectly (for example, as through a DSP). The phase relationship between MCLK and LRCK
should be kept after power-up. The MCLK frequencies shown in Table 1 are supported. The internal clock frequency is
set depending on the external MCLK frequency automatically.
MCLK
128fs
192fs
256fs
384fs
512fs
768fs
1024fs
1536fs
Fs
16k-192kHz
16k-192kHz
8k-128kHz
8k-96kHz
8k-48kHz
8k-48kHz
8k-32kHz
8k-24kHz
Table 1. MCLK Frequency
MS0642-E-01
- 10 -
2010/09