AK4103A_09 Datasheet, PDF (6/27 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit DIT

SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.75~5.25V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
3.584
Duty Cycle
dCLK
40
LRCK Timing
Frequency
fs
28
Duty Cycle at Slave Mode
dLCK
45
Duty Cycle at Master Mode
50
Audio Interface Timing
Slave Mode
BICK Period
tBCK
36
BICK Pulse Width Low
tBCKL
15
Pulse Width High
tBCKH
15
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
SDTI Hold Time
SDTI Setup Time
(Note 5)
tLRB
15
(Note 5)
tBLR
15
tSDH
8
tSDS
8
Master Mode
BICK Frequency
fBCK
64fs
BICK Duty
dBCK
50
BICK “↓” to LRCK
SDTI Hold Time
SDTI Setup Time
tMBLR
-20
tSDH
20
tSDS
20
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN “H” Time
tCSW
520
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCSS
50
tCSH
50
tDCD
(Note 6)
tCCZ
Power-down & Reset Timing
PDN Pulse Width
tPDW
150
Note 5. BICK rising edge must not occur at the same time as LRCK edge.
Note 6. CDTO pin is internally connected to a pull-down resistor.
[AK4103A]
max
27.648
60
192
55
Units
MHz
%
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
Hz
%
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
ns
70
ns
ns
MS0251-E-01
-6-
2009/01