AK5536 Datasheet, PDF (54/69 Pages) Asahi Kasei Microsystems – 6-Channel Differential 32-bit  ADC

[AK5536]
■ Power Up/Down Sequence
The AK5536 enters power-down mode by setting the PDN pin to “L”. Digital filters are reset at the same
time.
[1] PCM Mode
In slave mode, internal power down signal (Internal PDN) is released by inputting MCLK, BICK and
LRCK after setting the PDN pin to “H”. In master mode, The Internal PDN is released by inputting MCLK
after setting the PDN pin to “H”.
Initialization cycle starts when the Internal PDN is released. The output data of SDTO will be valid in 583
x 1/fs after exiting power-down mode in slave mode, it will be valid in 578 x 1/fs after exiting power-down
mode in master mode. During initialization, the ADC digital outputs of both channels are in 2’s
complement format and forced to “0”. The ADC outputs settle to data correspondent to the input signals
after the end of initialization. This settling takes approximately the group delay time.
Power
PDN pin
(1)
VDD18 pin
Internal PDN
(2)
Internal
State
Power -down
(3)
Initialize
Normal Operation
Power -down
ADC In
(Analog)
ADC Out
(Digital)
Clock In
Don’t care
MCLK,LRCK,BICK
(4)
“0”data
Idle Noise
(5)
GD
(5)
GD
Idle Noise
(4)
“0”data
Don’t care
Figure 59. Power-Up/Down Sequence Example
Notes
(1) The PDN pin should be held to “L” for more than 150 ns after AVDD and TVDD are powered up.
(2) a. LDOE pin = “H”, I2C pin = “H” and PSN pin = “H” (Parallel Mode):
The internal LDO is powered up by releasing PDN pin to “H”. The Internal PDN is released by
toggling MCLK for 16384times.
b. LDOE pin = “H” and PSN pin = “L” (Register Mode):
The internal LDO is powered up by releasing PDN pin to “H”. The internal PDN is released by
toggling internal oscillator clock for 16384 times (max. 10 ms).
c. LDOE pin = “L”:
The internal PDN is released in 1 ms (max.) after releasing PDN pin to “H”.
During this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1
us). Therefore, referring the output of digital pins and data transmission with a device on the same
3-wire serial/I²C bus as the AK5536 should be avoided in this period to prevent system errors.
(3) Initialization cycle is 583/fs in slave mode and 578/fs in master mode.
(4) The ADC output data is “0” during initialization cycle and power-down mode.
(5) The digital output corresponding to analog input has group delay (GD).
015099885-E-00
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2016/03