AKD4565 Datasheet, PDF (5/27 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4565

ASAHI KASEI
[AKD4565]
„ DIP Switch set up
[SW3] (MODE): Setting evaluation mode of CS8412(DIR)
ON is “1”, OFF is “0”.
AK4565
DIF1
DIF0
MODE
SW3
M0
M1
M2
0
0
16bit LSB justified
1
0
1
0
1
20bit LSB justified
N/A
1
0
20bit MSB justified
0
0
0
1
1
I²S Compatible
0
1
0
Table 2. AK4565 audio data I/F format and SW3 and JP6 Setting
SW3 and AK4565 format must be the same audio data format.
JP6
THR
INV
THR
„ Other jumper pins set up
1. JP1 (GND) : Analog ground and Digital ground
OPEN : Separated.
SHORT : Common. (The connector “DGND” can be open.) <Default>
2. JP2 (VT) : D2V and VT
OPEN : Separated. <Default>
SHORT : Common. (The connector “VT” can be open.)
3. JP6 (PHASE) : Phase of BCLK using DIR
THR : BCLK is coincides with AK4565. (16bit LSB justified and I²S compatible for DAC.)
INV : BCLK is inverted. (20bit MSB justified for DAC.)
4. JP7 (SDTO) : When JP9 (SDTI) is open, the A/D data can be output from the PORT3.
*Always open. When evaluation mode is “6)”, JP7 can be short.
5. JP8 (SD0/1) : Select SDTO0 or SDTO1
SD0 : Select SDTO0.
SD1 : Select SDTO1.
„ The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Power down of the AK4565. Keep “H” during normal operation.
[SW2] (DIT): Power down of the AK4353. Keep “H” during normal operation.
„ Indication for LED
[LED1] (VERF): Monitor VERF pin of the CS8412. LED turns on when some error has occurred to the CS8412.
[LED2] (PREM): Indicate whether the input data of the CS8412 is pre-emphasized or not.
<KM067001>
-5-
2002/01