AKD4565 Datasheet, PDF (2/27 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4565

ASAHI KASEI
[AKD4565]
EVALATION BOARD MANUAL
„ Operation sequence
1) Set up the power supply lines.
[VA] (orange) = 2.3 ∼ 3.6V : for VA of AK4565 (typ. 2.5V)
[VT]
(orange) = 1.5 ∼ 3.6V : for VT of AK4565 (typ. 2.5V)
[D2V] (orange) = 1.5 ∼ 3.6V : for 74LVC541 (typ. 2.5V)
[D5V] (red)
= 3.6 ∼ 5.0V : for logic (typ. 5.0V)
[AGND] (black)
= 0V
: for analog ground
[DGND] (black)
= 0V
: for logic ground
Each supply line should be distributed from the power supply unit.
VT and D2V must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4565 and AK4353(DIT) should be reset once bringing SW1, 2 “L” upon power-up.
„ Evaluation mode
Applicable Evaluation Mode
1) Evaluation of loopback mode <Default>
2) Evaluation of D/A using A/D converted data
3) Evaluation of D/A using DIR (Optical Link)
4) Evaluation of A/D using D/A converted data
5) Evaluation of A/D using DIT (Optical Link)
6) All interface signals including master clock are fed externally.
1) Evaluation of loopback mode. <Default>
Nothing should be connected to PORT3 and PORT4. In case of using external clock through a BNC
connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE). When SDTO0 is connected with SDTI,
JP8 (SD0/1) selects SD0 side. When SDTO1 is connected with SDTI, JP8 (SD0/1) selects SD1 side.
Does not support DIF1-0 = “01”.
DIF1
0
1
1
AK4565
DIF0 SDTO0/SDTO1 (ADC)
SDTI (DAC)
JP3 (X_BCLK)
0
20bit MSB justified
16bit LSB justified
32fs
0
20bit MSB justified
20bit MSB justified
64fs
1
I²S Compatible
I²S Compatible
32fs or 64fs
Table 1. AK4565 audio data I/F format and JP3 Setting
JP3
X_BCLK
JP4
LRCK
JP5
BCLK
JP9
SDTI
JP10
DIR
JP11
CLK
JP12
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
<KM067001>
-2-
2002/01