AKD4565 Datasheet, PDF (3/27 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4565

ASAHI KASEI
[AKD4565]
2) Evaluation of D/A using A/D converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3. MCLK, BCLK, LRCK and SDTO0/1 are sent from AKD4565
to AKM’s D/A evaluation boards. Nothing should be connected to PORT1, PORT4. In case of using
external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE).
JP3
X_BCLK
JP4
LRCK
JP5
BCLK
JP9
SDTI
JP10
DIR
JP11
CLK
JP12
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
3) Evaluation of D/A using DIR. (Optical link)
PORT4 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT1 and PORT3.
JP3
X_BCLK
JP4
LRCK
JP5
BCLK
JP9
SDTI
JP10
DIR
JP11
CLK
JP12
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
4) Evaluation of A/D using D/A converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT3. MCLK, BCLK and LRCK are sent from AKM’s D/A
evaluation board to AKD4565. Nothing should be connected to PORT4. When SDTO0 is supplied via
PORT1, JP8 (SD0/1) selects SD0 side. When SDTO1 is supplied via PORT1, JP8 (SD0/1) selects SD1 side.
JP3
X_BCLK
JP4
LRCK
JP5
BCLK
JP9
SDTI
JP10
DIR
JP11
CLK
JP12
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
<KM067001>
-3-
2002/01