AKD4382 Datasheet, PDF (5/26 Pages) Asahi Kasei Microsystems – EVALUATION BOARD REV.A FOR AK4382

ASAHI KASEI
[AKD4382]
n Jumpers set up
[JP1](TORX/BNC): The source of the biphase signal input to the AK4112A
TORX: PORT1(TORX176: optical link) <default>
BNC: J1(BNC)
[JP2](GND): AGND and DGND
Open: AGND and DGND are disconnected. <default>
Short: AGND and DGND are connected. ( “DGND” jack can be open.)
[JP3](REG): VDD of the AK4382
Short: VDD is supplied from the regulator ( “4382_VDD” jack should be open). <default>
Open: VDD is supplied from “4382_VDD” jack.
[JP4](MCLK): MCLK of the AK4382
Short: MCLK is fed from the AK4112A. <default>
Open : MCLK is fed from the external circuit via PORT2(EXT).
[JP5](BICK): BICK of the AK4382
Short: BICK is fed from the AK4112A. <default>
Open : BICK is fed from the external circuit via PORT2(EXT).
[JP6](SDATA): SDTI of the AK4382
Short: SDATA is fed from the AK4112A. <default>
Open : SDATA is fed from the external circuit via PORT2(EXT).
[JP7](LRCK): LRCK of the AK4382
Short: LRCK is fed from the AK4112A. <default>
Open : LRCK is fed from the external circuit via PORT2(EXT).
n The function of the toggle SW
[SW1] (PDN): Resets the AK4382 and the AK4112A. Keep “H” during normal operation.
n The indication content for LED
[LE1] (ERF) : Unlock and parity error output of the AK4112A.
[LE2] (FS96) : 96kHz sampling detect of the AK4112A.
[LE3] (AUTO) : Non-PCM data (AC-3, MPEG etc.) detects of the AK4112A.
[LE4] (V)
: Validity detect of the AK4112A.
n Serial control
The AKD4382 can be controlled via the printer port (parallel port) of
IBM-AT compatible PC. Connect PORT3(uP-I/F) with PC by 10-wire
flat cable packed with the AKD4382.
Take care of the direction of connector. There is a mark at 1pin.
The pin layout of PORT3 is as Figure 4.
PORT3
10 ^uP-I/F
9
CSN
CCLK
CDTI
2
1
Figure 4. PORT3 pin layout
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