AKD4382 Datasheet, PDF (3/26 Pages) Asahi Kasei Microsystems – EVALUATION BOARD REV.A FOR AK4382

ASAHI KASEI
[AKD4382]
n Operation sequence
1) Set up the power supply lines.
[+15V]
(orange) = +12 ∼ +15V
[-15V]
(blue) = -12 ∼ -15V
[4382_VDD] (red) = 4.75 ∼ 5.25V (Note 2)
[AGND] (black) = 0V
[DGND] (black) = 0V
Note: 1. Each supply line should be distributed from the power supply unit.
2. JP3(REG) should be shorted and “4382_VDD” jack should be open if VDD of the AK4382 is supplied
from the regulator.
2) Set-up the evaluation modes, jumper pins and DIP switches (See the followings.)
3) Power on.
The AK4382 should be reset once bringing SW1(PDN) “L” upon power-up.
n Evaluation mode
Applicable evaluation modes
1) DIR (Optical Link or BNC) (default)
2) Using ROM data (AK43XX)
3) Using AKM’s evaluation board for ADC
4) Feeding all signals from external
1) DIR (Optical Link or BNC) <default>
The AK4112A(DIR) generates MCLK, BICK, LRCK and SDATA from the received data through
PORT1(TORX176: optical link) or J1(BNC). Used for the evaluation using CD test disk. Nothing should be
connected to PORT2(EXT). In case of using optical connector (TORX176), JP1(TORX/BNC) should be selected
to “TORX”. In case of using BNC connector, select “BNC”.
JP4
JP5
JP6
JP7
MCLK
BICK SDATA LRCK
2) Ideal sine wave generated by ROM data
Connect the AKD43XX with PORT2(EXT). The AKD4382 sends MCLK to the AKD43XX which the
AK4112A(DIR) generates from the received data through PORT1(TORX176: optical link) or J1(BNC). And the
AKD4382 receives LRCK, BICK and SDATA from the AKD43XX.
JP4
JP5
JP6
JP7
MCLK
BICK SDATA LRCK
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