AKD4125 Datasheet, PDF (5/20 Pages) Asahi Kasei Microsystems – AK4125 Evaluation Board Rev.0

ASAHI KASEI
[AKD4125-A]
(2) All clocks are fed through the 10pin port
When using PORT3 (OUTPUT), nothing should be connected to J2 (TX) and PORT4 (DIT).
JP6
JP7
OBICK OLRCK
• SW4 setting (See Table 6)
Upper-side is “H” and lower-side is “L”.
SW4 No.
1
2
3
4
5
6
7
Name
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
OBIT1
OBIT0
ON (“H”)
OFF (“L”)
AK4125 Output Audio I/F Format Setting
Refer to Table 7
AK4125 Mode Setting
Refer to Table 8
AK4125 Output bit Length Setting
Refer to Table 9
Table 6. SW4 Setting
Default
H
L
H
L
L
H
H
Mode ODIF1 ODIF0 SDTO Format
0
L
L
LSB justified
1
L
H
(Reserved)
2
H
3
H
L
MSB justified
H
I²S Compatible
Table 7. Output Audio Interface Format 1 (Output PORT)
Mode
0
1
2
3
4
5
6
7
CMODE2
L
L
L
L
H
H
H
H
CMODE1 CMODE0 Master / Slave
OMCLK
L
L
Master
256fso
L
H
Master
384fso
H
L
Master
512fso
H
H
Master
768fso
L
L
Slave
Not used. Set to DVSS.
L
H
Master
128fso
H
L
Master
192fso
H
H
Master (Bypass) Not used. Set to DVSS.
Table 8. Master/Slave Control (Output PORT)
fso
8k ∼ 108kHz
8k ∼ 108kHz
8k ∼ 54kHz
8k ∼ 54kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
Mode
OBIT1
OBIT0 SDTO Output
0
L
L
16bit
1
L
H
18bit
2
H
L
20bit
3
H
H
24bit
Table 9. Output Audio Interface Format 2 (Output PORT)
<KM078700>
-5-
2005/06