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AKD4125 Datasheet, PDF (16/20 Pages) Asahi Kasei Microsystems – AK4125 Evaluation Board Rev.0
◁
A
E
D
C
B
PORT4
TOTX141
TX(OPT)
IN
VCC
3
2
GND 1
A
C31
0.1u
A
B
C
D
E
U4
1 IPS0
2 NC
3 DIF0
4 TEST2
5 DIF1
6 NC
7 DIF2
8 IPS1
9 P/SN
10 XTL0
11 XTL1
12 VIN
C26
0.1u
C28
10u
C21
10u
C22
0.1u
C23
0.47u
AK4114
C27
0.1u
C29
10u
REG
INT0 36
OCKS0 35
OCKS1 34
JP5 HIF3G-50P-2.54DSA (3x1)
CKSO
L
OMCLK
CM1 33
OBICK
CM0 32
PDN 31
XTI 30
XTO 29
DAUX 28
PDN
C24 (open)
X1 HC-49/U
11.2896MHz
C25
(open)
OLRCK
SDTO
MCKO2 27
BICK 26
JP6 HIF3G-50P-2.54DSA (2x1)
OBICK
SDTO 25
JP7 HIF3G-50P-2.54DSA (2x1)
OLRCK
DIF2 DIF1 DIF0
Setting
H L L 24bit, MSB justified
OCKS1 OCKS0
L
L
H
H
Setting
256fs, 96kHz
128fs, 192kHz
CM1
L
CM0
H
Setting
PLL=OFF, X'tal Mode
R25
100
R26
100
R27
100
R28
100
R29
220k
R30
220k
R31
220k
R32
220k
E
D
PORT3
A1-10PA-2.54DSA
OMCLK 1
10
OBICK 2
9
OLRCK 3
8
SDTO 4
7
5
6
OUTPUT
C
B
OPT
C30
R33
0.1u
240
BNC
JP8 HIF3G-50P-2.54DSA (3x1)
TX
T2
J2
DA-02F BNC-R-PC
TX(BNC)
R34
150
1:1
B
C
A
Title
AKD4125-A
Size
Document Number
Rev
A3
OUTPUT
0
Date: Monday, May 23, 2005
Sheet
3 of 3
D
E
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