AKD4125 Datasheet, PDF (3/20 Pages) Asahi Kasei Microsystems – AK4125 Evaluation Board Rev.0

ASAHI KASEI
[AKD4125-A]
(2) All clocks are fed through the 10pin port
When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR).
JP2
IBICK
JP3
SDTI
JP4
ILRCK
• SW3 setting (See Table 2)
Upper-side is “H” and lower-side is “L”.
SW3 No.
1
2
3
4
5
6
7
Name
DITH
PLL2
PLL1
PLL0
IDIF0
IDIF1
IDIF2
ON (“H”)
Dither ON
OFF (“L”)
Dither OFF
PLL Mode Setting
Refer to Table 3
AK4125 Audio I/F Format Setting
Refer to Table 4
Table 2. SW3 Setting
Default
L
H
L
H
L
H
L
Mode Master / Slave
0
1
2
Slave
IMCLK = DVSS
3
IBICK = Input
4
ILRCK = Input
5
6
7
8
9
10
Master
11 IMCLK = Input
12 ^{IBICK = Output}
13 ^{ILRCK = Output}
14
15
PLL2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
PLL1 PLL0 ILRCK Freq IBICK Freq IMCLK
L
L
8k ∼ 96kHz
L
H
8k ∼ 216kHz ^{Depending on Not}
16k ∼ 216kHz
IDIF2-0
needed.
H
L
(Note 1)
H
H
Reserved
L
L
32fsi (Note 3)
L
H
8k ∼ 216kHz
64fsi
Not
H
L
(Note 2)
128fsi
needed.
H
H
64fsi
L
L
8k ∼ 216kHz
128fs
L
H
8k ∼ 108kHz
256fs
H
L
8k ∼ 54kHz
512fs
H
H
8k ∼ 216kHz
64fs
L
L
8k ∼ 216kHz
128fs
192fs
L
H
8k ∼ 108kHz
384fs
H
L
8k ∼ 54kHz
768fs
H
H
8k ∼ 216kHz
192fs
Table 3. PLL Setting (Input PORT)
SMUTE
(Note 4)
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter” in the
datasheet. 470Ω, 0.22µF and 1nF are implemented on the evaluation board.
Note 2. The IBCIK must be continuous except when the clocks are changed.
Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I²S Compatible.
Note 4. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode in the datasheet.
<KM078700>
-3-
2005/06