AKD4112B Datasheet, PDF (5/17 Pages) Asahi Kasei Microsystems – AKD4112B EVALUATION BOARD

ASAHI KASEI
[AKD4112B]
2. Clock operation mode
Mode
0
1
2
3
CM1
0
0
1
1
CM0 UNLOCK PLL
X'tal Clock source SDTO
0
-
ON ON(Note)
PLL
RX
1
-
OFF
ON
X'tal
DAUX
0
ON
ON
0
1
ON
ON
PLL
RX
X'tal
DAUX
1
-
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Default
Table 2. Clock Operation Mode select
3. Audio interface format
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I²S
24bit, Left justified
24bit, I²S
SDTO
LRCK
I/O
16bit, Right justified H/L O
18bit, Right justified H/L O
20bit, Right justified H/L O
24bit, Right justified H/L O
24bit, Left justified
24bit, I²S
H/L O
L/H O
24bit, Left justified H/L I
24bit, I²S
L/H I
Table3. Audio Data Format
BICK
I/O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64-128fs I
64-128fs I
Default
<KM065901>
-5-
2002/12