AK2346B Datasheet, PDF (5/31 Pages) Asahi Kasei Microsystems – Two-way Radio Audio Processor

ASAHI KASEI
[AK2346B]
Block
AGND
OSC
Control
Register
Description
The circuit to generate the reference voltage (1/2VDD) for internal analog signal.
The circuit to oscillate the 3.6864MHz reference clock with an external crystal oscillator
and resistor and capacitors.
The control register controls the status of internal switches and digitally controlled
amplifiers of IC by serial data that consists of 3 address bits and 8 data bits. At the start
up a power-on-reset circuit works and “Reset” data are set to the control register. (Refer
to the control register map)
The data buffer stores 8 bits of the MSK received data to smooth the signal interface with
microprocessor.
6. Pin/Function
Package
Signal
Pin No Name Type
1 AGNDIN
I
2 AGND
O
3 TXIN
I
4 TXINO
O
5 LIMLV
I
6 EXTLIMIN I
7 MOD
O
8 VSS
PWR
9 TCLK
O
10 TDATA
I
11 DI/O
I/O
12 RDF/FD
O
Function
Analog ground input pin.
Connect the capacitor to stabilize the analog ground level. This pin also has
reset function for the registers. Connecting to the low level, “Reset” data are set
to the control register.
Analog ground output pin.
Connect the capacitor to stabilize the analog ground level.
Transmit audio signal input pin.
This is the inverting input pin for TXA1. It composes a microphone amplifier with
an external resister and capacitor.
TXA1 feedback output pin.
Limit level adjuster pin.
A limit level can be adjusted by applying a DC voltage to this pin. If it is open,
the level is fixed to a predetermined level.
External signal input pin pre-limiter circuit.
This pin is available for external tone signal.
The modulated transmit signal output pin.
Load impedance larger than 10kΩ can be drive.
Negative power supply pin.
Normally supply 0V to this pin.
Clock output pin for MSK transmission data.
Setting the register named TXSW2 to “0” puts out 1.2/2.4kHz clock. If the
register is set to “1”, it goes to High level.
MSK transmission data input pin.
Data are latched synchronizing with the TCLK rising edge.
Serial data input and output pin.
Input for register setting data and output for MSK receive data.
MSK signal received flag and frame detection signal output pin.
This pin puts out two types of signal that depends on the status of register
named FSL.
In case FSL equal “1”, it is received flag mode (RDF). So the pin puts out low
level after 8 bits of MSK receive signal have been written to the internal register.
In case FSL equal “0”, it is frame detection mode (FD). So the low pulse is put
out after a frame pattern is detected.
MS1409-E-00
-5-
2012/05