AK2346B Datasheet, PDF (25/31 Pages) Asahi Kasei Microsystems – Two-way Radio Audio Processor

ASAHI KASEI
[AK2346B]
(4) After 8 bit received data (MD7…0) have been entered to the internal buffer from node RDATA,
RDF/FD pin goes to low level as RDF mode.
(Point D)
(5) After CPU detects this low level at RDF/FD pin, please puts in 8 clock to SCLK pin. Then
modulated data (RD7…0) put out from DI/O pin synchronized with falling edge of SCLK clock.
(Interval E)
(6) After 8 clock have been put into SCLK pin completely, RDF/FD pin goes to high level that
shows all modulated data coming from DI/O pin.
(Point F)
(7) By repeating the steps (4), (5), (6), the data come out from DI/O pin continuously.
(8) After the necessary data have been read, DIR pin sets to high level and FCLN=0. Then
internal node RCLK and RDATA are set to “1” for initializing and system waits for the next
synchronization frame data.
(Interval G)
This frame detection circuit does not have reset function. In case of stopping the sequence
during the steps (1) to (8), please set again from the first step (1). Especially, when RDF/FD
pin goes out low level on frame detecting, FCLN register is sets to “1” automatically as written
in (2). If you set FCLN=0 during this operation, the date set “0” is ignored. So please set the
data again after RDF/FD pin puts out high level.
When frame detection is not used, please set FCLN=1 and FSL=1 from the beginning. In that
case, monitoring the low level put out from RDF/FD pin, then puts 8 clock into the SCLK pin as
written in step (4). In this sequence, please program the frame detecting operation by
microprocessor.
MS1409-E-00
- 25 -
2012/05