AK4438 Datasheet, PDF(48/63 Page) Asahi Kasei Microsystems – 108dB 768kHz 32bit 8-Channel Audio DAC

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AK4438 Datasheet, PDF (48/63 Pages) Asahi Kasei Microsystems – 108dB 768kHz 32bit 8-Channel Audio DAC

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[AK4438]

â Serial Control Interface

The AK4438âs functions are controlled through registers. The registers may be written by two types of

control modes. The internal registers are controlled in 3-wire serial control mode when the I2C pin = âLâ

and the PS pin = âLâ, and in I2C bus control mode when the I2C pin = âHâ and the PS pin = âLâ. Chip

address is determined by the CAD0 and CAD1 pins. The internal registers are initialized by setting the

PDN pin to âLâ. The internal timing circuit is reset by setting RSTN bit = â0â but register values are not

initialized..

*Register writings are not available when the PDN pin = âLâ.

(1) 3-wire Serial Control Mode (I2C pin = âLâ)

The internal registers may be written through the 3-wire ÂµP interface pins (CSN, CCLK and CDTI). The

data on this interface consists of a 2-bit Chip address, Read/Write (1bit, Fixed to â1â, Write only), Register

address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the

rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after

a low-to-high transition of CSN. The clock speed of CCLK is 5MHz (max).

The internal registers are initialized by setting the PDN pin = âLâ. In serial mode, the internal timing circuit

is reset by setting RSTN bit = â0â but register values are not initialized.

CSN

CCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CDTI

C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

C1-C0: Chip Address (C1=CAD1, C0=CAD0)

R/W: READ/WRITE (Fixed to â1â, Write only)

A4-A0: Register Address

D7-D0: Control Data

Figure 37. Control I/F Timing

* The AK4438 does not support read commands in 3-wire serial control mode.

* When the AK4438 is in power down mode (PDN pin = âLâ), a writing into the control registers is

prohibited.

* The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more

during CSN is âLâ.

016001925-E-00

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2016/03

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