AK4438 Datasheet, PDF (16/63 Pages) Asahi Kasei Microsystems – 108dB 768kHz 32bit 8-Channel Audio DAC

[AK4438]
Parameter
Symbol Min. Typ. Max. Unit
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
40
ns
CDTI Hold Time
tCDH
40
ns
CSN “H” Time
tCSW
150
ns
CSN “” to CCLK “”
tCSS
50
ns
CCLK “” to CSN “”
tCSH
50
ns
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA 0.6
SDA Hold Time from SCL Falling
(Note 18) tHD:DAT 0
SDA Setup Time from SCL Rising
tSU:DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO 0.6
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Capacitive load on bus
Cb
-
-
s
-
s
-
s
-
s
-
s
-
-
1.0
0.3
s
s
s
-
50
400
s
ns
pF
Power-down & Reset Timing
PDN Pulse Width
(Note 19)
tAPD 800
ns
PDN Reject Pulse Width
tRPD
50
ns
Note 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 19. The AK4438 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held
“L” for more than 800ns for a certain reset. The AK4438 is not reset by the “L” pulse less than
50ns.
Note 20. I²C-bus is a trademark of NXP B.V.
016001925-E-00
- 16 -
2016/03