AKD5702-A Datasheet, PDF (4/33 Pages) Asahi Kasei Microsystems – portable digital audio 16bit A/D converter

ASAHI KASEI
d) Set up jumper pins of SDTO
JP30
SDTO_SEL
JP29
SDTOB
[AKD5702-A]
A
B
(2) PLL Slave Mode 1 (PLL Reference CLOCK: MCKI pin)
* Connect PORT4 (DSP1) with DSP.
Figure below shows PORT4 pin assign.
PORT4
MCKI
BCLK
LRCK
SDTOA
VD
GND
GND
NC
NC
SDTOB
a) Set up jumper pins of MCKI clock
X’tal of 11.2896MHz (Default) is set on the AKD5702-A. In this case, the AK5702 corresponds to PLL reference
clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK5702 is supplied to a
divider (U3: 74VHC4040), EXT_BCLK and EXT_LRCK clocks are generated by the divider. Then “MCKO bit” in
the AK5702 should be set to “1”.
When an external clock is supplied through a BNC connector J1 (EXT_MCKI), select EXT_MCLK on JP16 (XTI)
and select EXT on JP7 (MCKI_SEL). JP12 (EXT) and R19 should be properly selected in order too match the output
impedance of the clock generator.
JP16
XTI
JP7
MCKI_SEL
JP5
TDMMCLK_SEL
JP32
MCLK_SEL
JP8
MKFS
MCKO EXT_MCLK DIT
EXT
MCKO EXT_MCLK
b) Set up jumper pins of BCLK clock
JP28
M/S
M
S
JP9
BCLKFS
JP10
BCLK_SEL
<KM086501>
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2007 / 04