AKD5700-A Datasheet, PDF (4/39 Pages) Asahi Kasei Microsystems – digital audio 16bit A/D converter

ASAHI KASEI
[AKD5700-A]
(2) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
*Connect PORT4 (DSP2) with DSP.
Figure below shows PORT4 pin assign.
PORT4
MCKI
EXBCLK
EXLRCK
EXSDTI
VD
GND
GND
NC
NC
SDTO
a) Set up jumper pins of MCKI clock
X’tal of 11.2896MHz (Default) is set on the AKD5700-A. In this case, the AK5700 corresponds to PLL
reference clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK5700 is
supplied to a divider (U3: 74VHC4040), EXBCLK and LRCK clocks are generated by the divider. Then
“MCKO bit” in the AK5700 should be set to “1”.
When an external clock is supplied through an RCA connector (J3: EXT/BCLK), select EXTCLK/BCLK on
JP16 (XTI) and select EXTCLK/BCLK on JP17 (MCLK_SEL). JP14 (EXT1) and R20 should be properly
selected in order too match the output impedance of the clock generator.
JP16
XTI
JP19
MCLK_SEL
JP11
MKFS
5700-
MCKO
EXTCLK
/BCLK
4114- MCKI EXTCLK
MCKO
/BCLK
256fs 512fs 1024fs MCKO
b) Set up jumper pins of BCLK clock
JP17
BCLK_SEL
JP12
BCLK
EXT EXT EXTBCLK/ BCLK/
BCLK
DIT
DIT
c) Set up jumper pins of LRCK clock
JP18
LRCK_SEL
64fs 32fs 16fs
JP13
LRCK
EXT EXT EXTLRCK/ LRCK/
LRCK DIT
DIT
2fs 1fs
<KM087000>
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2006 / 12