AKD5367A-A Datasheet, PDF (4/38 Pages) Asahi Kasei Microsystems – AK5367A Evaluation Board Rev.0

[AKD5367A-A]
(2) Master mode
(2-1) A/D evaluation using AK4104 DIT function
PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and it is output through optical
connector (TOTX141). It is possible to connect AKEMD’s D/A converter evaluation boards on the
digital-amplifier. The MCLK can be generated from crystal oscillator X1 or be input from J11 (BNC) or PORT2
(ROM).
(2-1-1) The MCLK is generated from crystal oscillator X1
Please set JP10 (CLK) “XTL”, open JP5 (LRCK), JP6 (BICK) and JP8 (XTE), short JP7 (MCLK) and JP9
(EXT). In this case, please do not connect anything with PORT2 (ROM).
JP5
JP6
JP7
JP8
JP9
JP10
LRCK BICK
MCLK
XTE
EXT
CLK
Figure 5. Switch Setting when the MCLK is Generated from Crystal Oscillator X1
(2-1-2) The MCLK input from BNC
Please set JP10 (CLK) “EXT”, short JP7 (MCLK) and JP8 (XTE), open JP5 (LRCK), JP6 (BICK) and JP9
(EXT). In this case, please do not connect anything with PORT2 (ROM).
JP5
JP6
JP7
JP8
JP9
JP10
LRCK BICK
MCLK
XTE
EXT
CLK
Figure 6. Switch Setting when the MCLK is Input from BNC
(2-1-3) The MCLK is input from PORT2
Please open JP5 (LRCK), JP6 (BICK), JP7 (MCLK), JP8(XTE), JP9(EXT) and JP10(CLK) when input the
external clock from PORT2 (ROM).
JP5
JP6
JP7
JP8
JP9
JP10
LRCK BICK MCLK
XTE
EXT
CLK
Figure 7. Switch Setting when the MCLK is Input from PORT2 (ROM)
(2-2) The A/D converter is evaluated with external AP equipment by using PORT2 (ROM)
<KM095000>
-4-
2008/06