AKD5367A-A Datasheet, PDF (3/38 Pages) Asahi Kasei Microsystems – AK5367A Evaluation Board Rev.0

[AKD5367A-A]
(1-1-1) The MCLK is generated from crystal oscillator X1
Please set JP10 (CLK) “XTL”, open JP8 (XTE), and short JP5 (LRCK), JP6 (BICK), JP7 (MCLK), JP9 (EXT).
MCLK can be selected to 256fs or 512fs with JP11 and JP12. In this case, please do not connect anything with
PORT2 (ROM).
JP5
JP6
JP7
JP8
JP9
JP10
LRCK BICK
MCLK
XTE
EXT
CLK
Figure 2. Switch Setting when the MCLK is Generated from Crystal Oscillator X1
(1-1-2) The MCLK is input from BNC
Please set JP10 (CLK) “EXT”, short JP5 (LRCK), JP6 (BICK), JP7 (MCLK) and JP8 (XTE), open JP9 (EXT).
MCLK can be selected to 256fs or 512fs with JP11 and JP12. In this case, please do not connect anything with
PORT2 (ROM).
JP5
JP6
JP7
JP8
JP9
JP10
LRCK BICK
MCLK
XTE
EXT
CLK
Figure 3. Switch Setting when the MCLK is Input from BNC
(1-1-3) The MCLK, BICK and LRCK input from PORT2
Please open JP5 (LRCK), JP6 (BICK), JP7 (MCLK), JP8(XTE), JP9(EXT) and JP10(CLK) when input the
external clock from PORT2 (ROM).
JP5
JP6
JP7
JP8
JP9
JP10
LRCK BICK MCLK
XTE
EXT
CLK
Figure 4. Switch Setting when the External Clock is Input from PORT2 (ROM)
(1-2) The A/D converter is evaluated with external AP equipment by using PORT2 (ROM)
The analog to digital conversion data can be transmitted from PORT2 (ROM). The clock can be generated from
crystal oscillator X1 or J11 (BNC) or PORT2 (ROM). Refer to (1-1-1), (1-1-2) and (1-1-3) to setting the
switches.
<KM095000>
-3-
2008/06