AKD4528_05 Datasheet, PDF (4/45 Pages) Asahi Kasei Microsystems – 24Bit A/D & D/A converter

ASAHI KASEI
[AKD4528]
„ Set-up SW2
[SW2]: Set-up AK4112B. Upper is “ON”(“H”), Lower is “OFF”(“L”)
(For further details, refer to the datasheet.)
No. Name
1 OCKS0
2 OCKS1
3 CM0
4 CM1
5 DIF0
6 DIF1
7 DIF2
Default
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
Set-up the master clock frequency (Default: 256fs)
(Refer to the datasheet.)
Set-up the clock source (Default: X’tal)
(Refer to the datasheet.)
Set–up the audio format (Default: 24bit, I²S )
(Refer to the datasheet.)
Table 1. Set up SW2
1. Set-up Master clock frequency
This master clock is generated by the AK4112B, and is supplied from MCKO1 pin of the AK4112B.
OCKS1 OCKS0
pin
pin
(SW2-2) (SW2-1) MCKO1
fs (kHz)
0
0
256fs 32, 44.1, 48, 96
0
1
256fs 32, 44.1, 48, 96
1
0
512fs 32, 44.1, 48
Table 2. Set up Master clock frequency
(Default)
2. Set-up Clock source
CM1
pin
(SW2-4)
0
0
CM0
pin
(SW2-3) PLL X'tal Clock source Input data of DAC
0
ON OFF
PLL
Optical
1
OFF ON
X'tal
Output of ADC (Default)
Table 3. Set up Clock source
(Note) ON: Oscillation (Power-up), OFF: STOP (Power-down)
3. Set–up Audio interface format
DIF2
pin
(SW2-7)
0
0
0
0
1
1
DIF1
pin
(SW2-6)
0
0
1
1
0
0
DIF0
pin
ADC format
Input format
(SW2-5) at Loopback
of DAC
0
24bit, Left justified 16bit, Right justified
1
24bit, Left justified 18bit, Right justified
0
24bit, Left justified 20bit, Right justified
1
24bit, Left justified 24bit, Right justified
0
24bit, Left justified 24bit, Left justified
1
24bit, I²S
24bit, I²S
Table 4. Set up Audio interface format
LRCK
H/L
H/L
H/L
H/L
H/L
L/H
BICK
64fs
64fs
64fs
64fs
64fs
64fs
(Default)
<KM063101>
-4-
2005/11