AKD4528 Datasheet, PDF (4/38 Pages) Asahi Kasei Microsystems – EVALUATION BOARD FOR AK4528 REV.C

ASAHI KASEI
[AKD4528]
n SW2 set-up (AK4112A set up. See datasheet of AK4112A.)
1. DIF2, DIF1 and DIF0 of SW2 set -up.
Set the mode of AK4112A
DIF2
0
0
0
0
1
1
DIF1
0
0
1
1
0
0
DIF0
0
1
0
1
0
1
ADC format
at Loopback
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I²S
Input format
of DAC
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I²S
LRCK
H/L
H/L
H/L
H/L
H/L
L/H
2. CM1and CM0 set-up
Clock source select of AK4112A
BICK
64fs
64fs
64fs
64fs
64fs
64fs default
CM1
0
0
CM0
0
1
PLL X'tal Clock source Input data of DAC
ON OFF
PLL
optical
OFF ON
X'tal
output of ADC
default
ON: Oscillation (Power-up), OFF: STOP (Power-down)
3. OCKS1 and OCKS0 set-up
MCLK output of AK4112A
OCKS1
0
0
1
OCKS0
0
1
0
MCKO1
256fs
256fs
512fs
fs (kHz)
32, 44.1, 48, 96
32, 44.1, 48, 96
32, 44.1, 48
default
<KM063100>
-4-
’00/06