AKD4384-SC Datasheet, PDF (4/32 Pages) Asahi Kasei Microsystems – 192kHz sampling 24Bit ΔΣ DAC

The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 4.
OCKS1
0
1
1
OCKS0
0
0
1
MCLK Frequency
256fs @fs=88.2/96kHz
512fs @32/44.1/48kHz
128fs @176.4/192kHz
Table 4. MCLK Clock
Default
SW1 setting
[SW1](PDN): Reset of AK4384. Select “H” during operation.
[AKD4384-SC]
<KM079003>
4
2007/06