AK5383 Datasheet, PDF (4/20 Pages) Asahi Kasei Microsystems – Enhanced Dual bit 96 kHz 24-bit ADC

ASAHI KASEI
[AK5383]
14 SCLK
15 SDATA
16 FSYNC
17 MCLK
18 DFS
19 HPFE
20 TEST
21 BGND
22 AGND
23 VA
24 AINR-
25 AINR+
26 VCOMR
27 GNDR
28 VREFR
I/O Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
O Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
I/O Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA. In I²S mode, FSYNC is
Don’t care.
Master mode:
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
I Master Clock Input Pin
256fs at DFS="L", 128fs at DFS="H".
I Double Speed Sampling Mode Pin
"L": Normal Speed
"H": Double Speed
I High Pass Filter Enable Pin
"L": Disable
"H": Enable
I Test Pin ( pull-down pin)
Should be connected to GND.
- Substrate Ground Pin, 0V
- Analog Ground Pin, 0V
- Analog Supply Pin, 5V
I Rch Analog negative input Pin
I Rch Analog positive input Pin
O Rch Common Voltage Pin, 2.75V
- Rch Reference Ground Pin, 0V
O Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10µF electrolytic capacitor and a 0.1µF
ceramic capacitor
Note: All digital inputs should not be left floating.
M0049-E-03
-4-
2000/4