AK5383 Datasheet, PDF (11/20 Pages) Asahi Kasei Microsystems – Enhanced Dual bit 96 kHz 24-bit ADC

ASAHI KASEI
[AK5383]
n System Clock Input
OPERATION OVERVIEW
The external clocks which are required to operate the AK5383 are MCLK, LRCK(fs), SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. MCLK should be 256fs in normal sampling mode(DFS="L") and
double sampling mode needs 128fs as MCLK. Table 2 illustrates standard audio word rates and corresponding frequencies
used in the AK5383.
As the AK5383 includes the phase detect circuit for LRCK, the AK5383 is reset automatically when the synchronization
is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
All external clocks must be present unless RST ="L", otherwise excessive current may result from abnormal operation of
internal dynamic logic.
Speed
LRCK (max)
SCLK
MCLK
Normal(DFS ="L")
54kHz
~128fs
256fs
Double(DFS ="H")
108kHz
~64fs
128fs
Table 1. System Clocks
fs
32.0kHz
44.1kHz
48.0kHz
96.0kHz
MCLK
8.1920MHz
11.2896MHz
12.2880MHz
12.2880MHz
SCLK
4.0960MHz
5.6448MHz
6.1440MHz
6.1440MHz
Table 2. Examples of System Clock Frequency
n Serial Data Interface
The AK5383 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 3). The data
format is MSB-first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE2
L
L
H
H
SMODE1
L
H
L
H
Mode
Slave Mode
Master Mode
I²S Slave Mode
I²S Master Mode
LRCK
Lch = H, Rch =L
Lch =H, Rch =L
Lch =L, Rch =H
Lch =L, Rch =H
Table 3. Serial I/F Format
M0049-E-03
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