AK5383 Datasheet, PDF (12/20 Pages) Asahi Kasei Microsystems – Enhanced Dual bit 96 kHz 24-bit ADC

ASAHI KASEI
[AK5383]
LRCK(i)
SCLK(i)
FSYNC(i)
0 1 23
SDATA(o)
23 22 21
20 21 22 23 24 25 15
43 2 1 0
Lch Data
0 12 3
20 21 22 23 24 25
23 22 21 7 4 3 2 1 0
Rch Data
01
23 22
FSYNC(i)
SDATA(o)
23 22
54 3 2 1 0
23 22
5432 10
23
23:MSB,0:LSB
Figure 1. Serial Data Timing (Slave Mode)
LRCK(o)
SCLK(o)
0 1 23
20 21 22 23 24 25 15 33 34
0 12 3
20 21 22 23 24 25
FSYNC(o)
SDATA(o)
23 22
54 3 2 1 0
23 22
5 4 3 21 0
Lch Data
Rch Data
23:MSB,0:LSB
Figure 2. Serial Data Timing (Master mode, DFS="L")
33 34
01
23
LRCK(i)
SCLK(i)
0 1 23
19 20 21 22 23 24
0 12 3
19 20 21 22 23 24
SDATA(o)
23 22
65 4 3 2 1 0
23 22
6543 210
Lch Data
Rch Data
23:MSB,0:LSB
Figure 3. Serial Data Timing (I²S Slave mode, FSYNC: Don’t care.)
01
23
LRCK(o)
SCLK(o)
0 1 23
20 21 22 23 24 25 15 33 34
0 12 3
20 21 22 23 24 25
FSYNC(o)
SDATA(o)
23 22
54 3 2 1 0
23
23 22
5 4 3 21 0
Lch Data
Rch Data
23:MSB,0:LSB
Figure 4. Serial Data Timing (I²S Master mode, DFS="L")
33 34
01
23
M0049-E-03
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