AK2365 Datasheet, PDF (4/31 Pages) Asahi Kasei Microsystems – dPMR Filterless IF LSI

[AK2365]
Block
MIX
AGC+BPF
IFBUF
Divider
Limiter
DISCRI
LPF
Noise AMP
Noise Rectifier
Comparator
RSSI
VIREF
LDO
Control Logic
4. Circuit Configuration
Description
2nd-mixer to convert the input signal down to 450kHz.
The circuit composed of AGC and BPF, where the desired signal is amplified and
spurious components included in the signal from the 2nd-mixer are eliminated.
The circuit to output filtered signal by AGC+BPF.
The circuit to divide the signal from LOIN pin.
The circuit to amplify the signal filtered at the AGC+BPF stage and generate rectangular
wave.
The demodulator circuit with PLL FM detector, where the audio signal is recovered.
The Low-pass filter to eliminate the noise generated at the DISCRI stage.
The amplifiers to compose the Band-pass filter for noise squelch.
The rectification circuit to detect the noise level.
The circuit to compare the noise level with reference voltage level.
The circuit to indicate the Received Signal Strength Indicator (RSSI) by generating a DC
voltage corresponding to the input level from Limiter.
The circuit to generate internal reference voltage.
The circuit to supply 2.7V power for some circuits.
The control register controls the status of internal condition by serial data that consists of
1 instruction bit, 6 address bits and 8 data bits.
MS1453-E-01
-4-
2012/10