AK2363 Datasheet, PDF (4/33 Pages) Asahi Kasei Microsystems – Radio Signaling LSI

ASAHI KASEI
[AK2363]
Block Functions
Block
MSK Modulator
MSK DAC
MSK LPF
VR
TXA
RXA
MSK BPF
Data Demodulator
Digital PLL
AGC(PGA)
DTMF Receiver
Function
This circuit generates an MSK signal according to the logic of a digital signal input
from the TDATA pin.
DAC that converts data generated by the MSK Modulator into an analog signal.
This circuit is a low-pass filter for eliminating the clock component included in the
MSK DAC signal.
A switch for changing between the mute and active states is provided between this
filter and VR and is set by setting register MSKTX.
This control adjusts the output level of the transmit MSK signal.
Setting register: VR[4:0] Adjustment range: -6.0dB to +6.0dB in 0.5dB steps
Operational amplifier for gain adjustment of the transmit MSK signal and for forming
a smoothing filter for removing noise components included in the output signal.
Use an external resistor and capacitor to set the gain to 0dB and the cut-off
frequency to around 13kHz.
Operational amplifier for gain adjustment of the receive demodulation signal and for
forming a filter for preventing aliasing noise in the SCF circuit in the subsequent
stage. Use external resistors and capacitors to set the gain to 20dB or less and the
cut-off frequency to around 40kHz.
Band-pass filter to eliminate out-of-band components included in the receive MSK
signal.
This circuit demodulates the MSK signal and generates data.
This circuit detects the carrier signal from the MSK signal and regenerates a clock
signal.
AGC (Auto Gain Control) circuit for adjusting the input level of the DTMF signal
automatically.
Setting register: AGCSW or AGCSW. When disabled, this circuit functions as a
PGA (Programmable Gain Amp) circuit.
Setting register: PGA[1:0] Adjustment range: 0dB to +12dB in 4dB steps
A switch for changing the input is provided between this circuit and RXA and is set
by setting register DTMFSL.
DTMF signal detection circuit. It decodes the input signal and outputs 4-bit code.
OSC
DIV (1/2,1/3,1/4)
AGND
Control
Register
This circuit generates a 3.6864MHz reference clock signal from an external crystal
oscillator and resistor.
When a signal of which frequency is twice, three times, or four times higher than
3.6864MHz is input from the outside, this circuit divides the signal frequency by two,
three, or four.
Setting register: MCKSL[1:0]
This circuit generates the reference voltage (1/2VDD) for internal analog signals.
Control registers set the switches and control in the IC according to the serial input
data consisting of a 1-bit instruction, a 4-bit address, and 8-bit data. A built-in data
buffer is provided to hold 8-bit MSK receive data for easier interfacing with the CPU.
At power-on, a system reset is caused by the RSTN pin. A soft reset is set by the
SRST register. (Refer to the description of the registers.)
MS0583-E-01
-4-
2008/06