AK2363 Datasheet, PDF (23/33 Pages) Asahi Kasei Microsystems – Radio Signaling LSI

ASAHI KASEI
[AK2363]
2) MSK Demodulator
2.1) When Frame Detect is not used
The modem interfaces with the Demodulator by using the RXIN, RCLK, and RDFFD/RDATA
pins, register data BS[2:0], and MSKRCLK as follows:
(1) Set BS[2:0] to select mode 3, 4, or 6, and at the same time set MSKRCLK to 1 to start MSK
reception.
(2) When the MSK signal is received on the RXIN pin, data demodulated via MSK-BPF,
Data-Demodulator, and the Digital-PLL circuit is output successively as RDATA on the
RDFFD/RDATA pin in synchronization with the falling edge of the 1200Hz or 2400Hz clock
signal output on the RCLK pin.
(3) Set BS[2:0] to select mode 0, 1, 2, or 5. The MSK signal reception operation then ends.
2.2) When Frame Detect is used
The modem interfaces with the Demodulator by using the RXIN, RDFFD/RDATA, SDATA,
SCLK, and CSN pins, and register data BS[2:0], MSKRCLK, FSL, and FCLN as follows:
(1) Set BS[2:0] to select mode 3, 4, or 6, and at the same time set MSKRCLK to 0, FSL to 0, and
FCLN to 0 to start MSK reception. This setting allows the RDFFD/RDATA pin to function as
RDFFD frame detection (FD) and output the high level, waiting for a synchronized frame.
At this time, the CSN pin is set to the high input level, and the SCLK pin is set to the low input
level.
(2) When a synchronized frame is detected, the RDFFD/RDATA pin performs a frame detection
(FD) operation. The pin is at the low output level during period T, and FCLN data is set to 1
automatically.
(3) When the low level on the RDFFD/RDATA pin is monitored, set FSL to 1 so that the MSK
receive flag signal (RDF) is output.
(4) After 8-bit receive data (MD7 to MD0) is transferred from internal node RDATA_n to the buffer, the
RDFFD/RDATA pin is set to the low output level as an RDF operation.
(5) When the CPU monitors this change, demodulated data (RD7 to RD0) is read from the
modem receive data register (address: A[3:0] = 0110).
(6) After the data has been read from the modem receive data register, the RDFFD/RDATA pin is
set to the high output level, indicating that data RD7 to RD0 in the buffer has all been read.
(7) By repeating steps (4), (5), and (6) above, demodulated data can be read from the receive data
register.
(8) After completing read of necessary data, set FCLN to 0. Then, internal nodes RCLK and
RDATA are initialized, and the system waits for another synchronized frame.
(9) Set BS[2:0] to select mode0, 1, 2, or 5. The MSK signal reception operation then ends.
This frame detection circuit does not have a reset feature. Therefore, if the above steps (1) to (8) are
canceled in the middle, the steps must be restarted from (1). As mentioned in (2), while the
RDFFD/RDATA pin is at the low output level as a result of frame detection (FD), the FCLN data is set to 1
automatically. During this period, an attempt to write 0 is ignored. Setting must be made again after the
RDFFD/RDATA pin is set to the high output level.
MS0583-E-01
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2008/06