AK2300 Datasheet, PDF (4/19 Pages) Asahi Kasei Microsystems – 3.3V Single channel PCM CODEC LSI

[AK2300]
Pin types
DIN: Digital input
AIN: Analog input
Pin#
Name
7
VFTN
6
GST
4
VR
14
FS
5
BCLK
11
DX
16
DR
1
MUTEN
2
PDN
13
DIF0
5
DIF1
3
VDD
12
LVDD
10
VSS
8
VREF
9
PLLC
Exposed
Pad
PIN FUNCTION
DOUT: Digital output
AOUT: Analog output
PWR: Power / Ground
Type
Function
Negative analog onput of analog input OP amp.
AIN Signgle-end amplifire is composed the exernal registers. Transmit gain is
defined by the ratio of the external registers.
AOUT
Output of the transmit OP amp.
The external feedback resister is connected between this pin and VFTN.
AOUT
Analog output of the D/A converter equivalent to the received PCM
code.
Frame sync input
DIN This clock is input for the internal PLL which generates the internal system
clocks. FS must be 8kHz clock which synchronized with BCLK.
Bit clock of PCM data interface
This clock defines the input/output timing of DX and RX.
DIN The frequency of BCLK should be 64kHz ´ N (N=1~32) and duty should be
40~60%. When this pin is taken low, power down the device.
*Please don’t stop BCLK at “H” level.
Serial output of PCM data
DOUT The PCM data is synchronized with BCLK. This output remains in the low
level except for the period in which PCM data is transmitted.
DIN
Serial input of PCM data
The PCM data is synchronized with BCLK.
DIN
Mute setting pin
“L” level forces both A/D, D/A output to mute state.
DIN
Power down setting pin
“L” level forces power down mode.
Audio data interface select pin
DIN ”L”=A-law,”H”=m-law,“FS”=Linear PCM
(Please connect DIF0 with FS(#14) at a Linear PCM mode.)
Audio data interface timing select pin
“H” : MSB of DX/DR are input/output by rising edge of FS.(Connect to VDD)
DIN “L” : MSB of DX/DR are input/output by next rising edge of BCLK after the
rising edge of FS.
(Please connect it with VDD when DIF1 is “H”.)
PWR Positive supply voltage
PWR Positive supply voltage for digital interface
PWR Ground (0V)
Analog reference voltage output
AOUT External capacitance (0.1mF) should be connected between this pin and
VSS. Please do not connect external load to this pin.
PLL loop filter output
AOUT External capacitance (0.056mF±30%: Includes temperature characteristic)
should be connected between this pin and VSS.
-
Flip side PAD
VSS or Open
<MS0998-E-00>
4
2008/9