AK2300 Datasheet, PDF (14/19 Pages) Asahi Kasei Microsystems – 3.3V Single channel PCM CODEC LSI

[AK2300]
FUNCTIONAL DESCRIPTIONS
PCM CODEC
- A/D
Analog input signal is converted to 14bit PCM data. The analog signal is fed to the anti-aliasing filter
(AAF) before the converting PCM data, to prevent signals around the sampling rate from folding back
into the voice band. The converted PCM data passes through the band limiting filter which Frequency
response is designated in page8, and output from the DX pin with MSB first format. It is synchronized
with rising edge of the BCLK. This PCM data is 8bit A/u-law or 14bit linear. And full scale is defined
as 3.14dBm0. The analog input of 0.660Vrms is converted to a digital code of 3.14dBm0.
- D/A
Input PCM data from the DR pin is through the digital filter which Frequency response is designated in
page8, and converted analog signal. This analog signal is removed the high frequency element with
SMF (fc=30kHz typ) and output from the VR pin. The input PCM data is 8bit A/u-law data or 14bit linear.
And full scale is defined as 3.14dBm0. When the input signal is 3.14dBm0, the level of the analog output
signal becomes 0.660Vrms.
- 14bit linear PCM digital code
The relation ship between the analog signal and the 14bit linear code.
Signal level
+Full code
Peak value of the PCM 0dBm0 CODEC
PCM 0-CODE
-Full scale
14bit linear CODE (MSB First)
01 1111 1111 1111
01 0110 0100 1010
00 0000 0000 0000
10 0000 0000 0000
PCM Data Interface
AK2300 supports the following PCM data formats
- DIF0=”L” : A-Law
- DIF0=”H”: u-Law
- DIF0=”FS”: Linear PCM
- DIF1=”H” : MSB of DX/DR are input/output by rising edge of FS
- DIF1=”L” : MSB of DX/DR are input/output by next rising edge of BCLK after the rising edge of FS.
PCM data is interfaced through the pin (DX, DR).
In each case, PCM data is interfaced by A/u-law data with 8bit format and 2’s compliment 2digit data with
16bit MSB first format. However, internal CODEC is 14bit format operation, then the lowest 2bits output
become to “L” level. For the input, the lowest 2bits are ignored.
- Frame sync signal （FS）
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface.
All the internal clock of the LSI is generated based on this FS signal.
-Bit clock （BCLK）
BCLK defines the PCM data rate. BCLK rate is 64kHz ´ N (N=1~32). This clock must be synchronized with
FS.
<MS0998-E-00>
14
2008/9