AK5397 Datasheet, PDF (36/44 Pages) Asahi Kasei Microsystems – 32-Bit Stereo Premium ADC

[AK5397]
■ Power Down & Reset
The AK5397 is placed in the power-down mode by bringing the PDN pin “L” and the digital filter is also
reset at the same time. This reset should always be made after power-up. In the power-down mode, the
VCOM is AVSS level. An analog initialization cycle starts after exiting the power-down mode. The output
data SDTO1/2 are valid after 1028 cycles of LRCK clock in master mode (1029 cycles in slave mode).
During initialization, the ADC digital data outputs of both channels are forced to “0”. The ADC outputs
settle to data correspondent to the input signals after the end of initialization (This settling takes
approximately the group delay time).
The AK5397 should be reset once by bringing the PDN pin “L” after power-up. The AK5397 exits reset
and power down state by MCLK rising edge after setting the PDN pin to “H”. The internal timing starts
clocking by the rising edge (falling edge in I2S mode) of LRCK after exiting reset and power down state
by MCLK.
PDN
VCOM
Internal
State
A/D In
(Analog)
A/D Out
(Digital)
OVF
(1)
(2)
Normal Operation
GD ₍₃₎
Power-down
Idle Noise
(4)
“0”data
“0”data
Initialize
“0”data
“0”data
Normal Operation
GD
Idle Noise
Notes:
(1) 1030/fs in slave mode, 1031/fs in master mode.
(2) The VCOM voltage reaches 2.5V in 1.53 ms (typ), 2.64ms (max) after the PDN pin = “H”.
(3) Analog output corresponding to digital input has group delay (GD).
(4) ADC and OVF outputs are “0” data in the power-down mode.
Figure 38. Power-down/up sequence example
014011535-E-00
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2014/11