AK5397 Datasheet, PDF (23/44 Pages) Asahi Kasei Microsystems – 32-Bit Stereo Premium ADC

[AK5397]
9. Functional Descriptions
■ System Clock
MCLK, BICK and LRCK (fs) clocks are required in slave mode. A stable clock must be supplied when the
AK5397 is in operation (PDN pin = “H”). The LRCK clock input must be synchronized with MCLK,
however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the
system clock frequency. MCLK frequency, BICK frequency and master/slave mode are selected by
CKS2-0 and MSN pins as shown in Table 2.
The MSN pin controls Master/Slave mode switching. The AK5397 outputs BICK and LRCK in master
mode when inputting MCLK. When the AK5397 is in slave mode, MCLK, BICK and LRCK should be
input. (Table 4)
For synchronization between multiple devices, the AK5397 should be reset by the PDN pin after an
operation clock change, clock mode switching, digital I/F change and Master/Slave mode switching.
Clock and Mode changes should only be made during the reset.
fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
384kHz
768kHz
MCLK
32fs
64fs
128fs
256fs
N/A
N/A
N/A
8.192MHz
N/A
N/A
N/A
11.2896MHz
N/A
N/A
N/A
12.288MHz
N/A
N/A
N/A
24.576MHz
N/A
N/A
24.576MHz
N/A
N/A
24.576MHz
N/A
N/A
24.576MHz
N/A
N/A
N/A
Table 1. System Clock Example (N/A: Not Available)
512fs
16.384MHz
22.5792MHz
24.576MHz
N/A
N/A
N/A
N/A
014011535-E-00
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2014/11