AK5397 Datasheet, PDF (32/44 Pages) Asahi Kasei Microsystems – 32-Bit Stereo Premium ADC

[AK5397]
When using multiple devices in slave mode on cascade connection, internal operation timing of each
device may differ for one MCLK cycle depending on PDN, MCLK and BICK input timings. To prevent this
timing difference, BICK “↓” should be more than ± 10ns from MCLK “↑” and PDN “↑” should be more than
± 15ns from MCLK “↑” as shown in Table 7.
This timing can be achieved by inputting BICK divided half on MCLK “↓” when MCLK=2 x BICK (Normal
512fs, Double Speed) (Figure 33), and can be achieved by inputting BICK synchronized to MCLK when
MCLK=BICK (Normal 256fs mode, Quad speed) (Figure 34).
Parameter
MCLK “” to BICK “↓”
BICK “↓” to MCLK “”
MCLK “↑” to PDN “↑”
PDN “↑” to MCLK “↑”
Symbol
min
typ
tMCB
10
tBIM
10
tMPD
15
tPDM
15
Table 7. TDM Mode Clock Timing
max
Unit
ns
ns
ns
ns
VIH
MCLK
VIL
tMCB tBIM
VIH
BICK
VIL
Figure 33. Audio Interface Timing (Slave mode, TDM Mode MCLK=2 x BICK)
VIH
MCLK
VIL
tMCB
tBIM
VIH
BICK
VIL
Figure 34. Audio Interface Timing (Slave mode, TDM Mode MCLK=BICK)
PDN
MCLK
VIH
VIL
tMPD
VIH
VIL
tPDM
Figure 35. Reset Timing (Slave mode, TDM Mode)
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