AK1542A Datasheet, PDF (33/37 Pages) Asahi Kasei Microsystems – 20 to 600MHz Integer-N Frequency Synthesizer

[AK1542A]
14. Typical Evaluation Board Schematic
AK1542A
100pF
REFIN
CP
220nF
VREF
Loop Filter
R3
C1 _R2'
R2
C3
SWIN
CPZ
BIAS
27k
RFINP
RFINN
C2
100pF
51
100pF
RFOUT
100pF
18
VCO
18
18
Fig. 14 Typical Evaluation Board Schematic
Note 1) The [CPZ] pin should be connected to the R2 and C2, which are intermediate nodes, even if the Fast Lock Up is
not used. Therefore, R2 must be connected to the [CP] pin, while C2 must be connected to the ground.
Note 2) In Fast Lock Up mode, R2 and R2’ are connected in parallel by internal switching. For calculation of loop band
width and phase margin at Fast Lock Up mode, the resistance should be considered as parallel of R2 and R2’.
Note 3) It is recommended that the exposed pad at the center of the backside should be connected to the ground.
Note 4) Test pins (TEST1 to 3) should be connected to the ground.
MS1399-E-00
- 33 -
2012/3