AK1542A Datasheet, PDF (17/37 Pages) Asahi Kasei Microsystems – 20 to 600MHz Integer-N Frequency Synthesizer

[AK1542A]
5. Reference Input
The reference input could be set to a dividing number in the range of 4 to 16383 using {R[13:0]}, which is a 14-bit address of
D[13:0] in <Address3>. A dividing number from 0 to 3 could not be set.
6. Prescaler and Swallow Counter
The dual modular prescaler (P/P+1) and the swallow counter are used to provide a large dividing ratio. The prescaler is set by
{PRE[1:0]}, which is a 2-bit address of D[15:14] in <Address3>.
{PRE[1:0]}=”00”: P=8, dividing ratio = 8/9
{PRE[1:0]}=”01”: P=16, dividing ratio = 16/17
{PRE[1:0]}=”10”: P=32, dividing ratio = 32/33
{PRE[1:0]}=”11”: Prohibited
7. Power Save Mode
AK1542A can be operated in the power-down or power-save mode as necessary by using the external control pins [PDN1]
and [PDN2].
Power On
See “13. Power-up Sequence”. It is necessary to bring [PDN1] to “High” first, then [PDN2]. Bringing [PDN1] and [PDN2]
to “High” simultaneously is prohibited.
Normal Operation
Pin name
PDN1
PDN2
State
“Low”
“Low” Power down
“Low”
“High” Prohibited
“High”
“Low” Power save Mode Note 1) and Note 2)
“High” “High” Normal Operation
Note 1) Register setup can be made 50µs after [PDN1] is set to “High”. The charge pump is in the Hi-Z state.
Note 2) Register settings are maintained when [PDN2] is set to “Low” during normal operation.
MS1399-E-00
- 17 -
2012/3