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AK1542A Datasheet, PDF (32/37 Pages) Asahi Kasei Microsystems – 20 to 600MHz Integer-N Frequency Synthesizer | |||
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2. Power-up Sequence
[AK1542A]
PVDD,CPVDD
PDN1
On-chip LDO
0V
(1.8V)
Refin
50ïs
1.8V
Refin must be input before setting [PDN2] to âHighâ
Donât care
input
Write to register
PDN2(PLL)
CP
H or L
Registers can be written
After more than 50ïs from the [PDN1] is set to âHighâ
Here [PDN1] is set to âHighâ after or at the same time as power-up.
HiZ
Output(*1)
*1 CP output is not defined before writing the data in
all addresses of the register. After writing them,
CP output can be controlled by register.
Fig. 13 Power Sequence
MS1399-E-00
- 32 -
2012/3
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