AK4364 Datasheet, PDF (31/34 Pages) Asahi Kasei Microsystems – 96kHz 24BIT DAC WITH PLL AND DIT

ASAHI KASEI
[AK4364]
SYSTEM DESIGN
Figure 13 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Condition: AVDD=DVDD=5V(TTL mode), PLL mode, I2C mode, Chip Address = “00”
Optical
27MHz
Decoder
Reset
uP
Analog 5V
5
10u 0.1u
+
1 MCKO
2 TX
3 DVDD
4 DVSS
DZF 24
5.1k (Note)
FLT 23
0.1u 10u ^0.22u
AVDD 22
+
AVSS 21
5 MCKI
6 BICK
7 SDTI
8 LRCK
AK4364
VCOM
20
+
0.1u 10u
AOUTL 19
AOUTR 18
Top View CAD1 17
+
Lch
Lch MUTE
Out
10u
220
27k
9 PDN
10 CSN
11 SCL
CAD0 16
I2C 15
TTL 14
+
10u
220
Rch MUTE
Rch
Out
27k
12 SDA
TST 13
System Ground
Analog Ground
Figure 13. Typical Connection Diagram
Note:This resister can be changed to 10kΩ if the distortion at low frequency (around 1kHz) is critical.
However the distortion at high frequency degrades in this case.
MS0014-E-01
- 31 -
2000/07