AK4364 Datasheet, PDF (18/34 Pages) Asahi Kasei Microsystems – 96kHz 24BIT DAC WITH PLL AND DIT

ASAHI KASEI
[AK4364]
The sub-frame is defined in the figure below:
- Bits 0-3 of the sub-frame represent a preamble for synchronization. There are three preambles:
The block preamble, B, is contained in the first sub-frame of Frame 0.
The channel 1 preamble, M, is contained in the first sub-frame of all other frames.
The channel 2 preamble, W, is contained in all of the second sub-frames.
Table 5 defines the symbol encoding for each of the preambles.
- Bits 4-27 of the sub-frame contain the 24 bit audio sample in 2’s complement format with bit 27 as the most
significant bit (MSB). For 16 bit mode, Bits 4-11 are all 0.
- Bit 28 is the validity flag. This is equal to V bit in the register.
- Bit 29 is a user data bit. This is always “0” in the AK4364.
- Bit 30 is a channel status bit. Frame 0 contains the first bit of the 192 bit word with the last bit in frame 191.
- Bit 31 is an even parity bit for bits 4-31 of the sub-frame.
0
34
L
Sync S
B
Audio sample
Figure 8. Sub-frame format
27 28 29 30 31
M
SVUC P
B
The block of data contains consecutive frames transmitted at a bit rate of 64 times the sample frequency, fs.
Preamble
B
M
W
Preceding state = 0
11101000
11100010
11100100
Preceding state = 1
00010111
00011101
00011011
Table 5. Sub-frame preamble encoding
Figure 9 shows the relation between input data to SDTI pin and audio data on sub-frame.
4
27
L
M
Sub-frame _S
Audio sample
S
B
B
Mode 0
0
15
Mode 1
012
17
Mode 2
01234
19
Mode 3,4,5 0 1 2 3 4 5 6 7 8
23
Figure 9. Relation between input data to SDTI pin and audio data on sub-frame
MS0014-E-01
- 18 -
2000/07