AK4364 Datasheet, PDF (17/34 Pages) Asahi Kasei Microsystems – 96kHz 24BIT DAC WITH PLL AND DIT

ASAHI KASEI
[AK4364]
LRCK
BICK
(32fs)
SDTI
01
23
11 12 13 14 15 0 1
2
3
11 12 13 14 15 0 1
8 23 22
13 12 11 10 9 8 23 22
13 12 11 10 9 8 23
BICK
(64fs)
SDTI
0123
23 24 25
31 0 1 2 3
23 24 25
31
0
1
23 22
1 0 Don’t care
23 22
1 0 Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 5 Timing
n TX Output Format
Data input via SDTI pin is formatted in digital interface format and output via TX pin. Data transmitted on the TX output
is formatted in blocks as shown in figure 6. Each block consists of 192 frames. A frame of data contains two sub-frames.
A sub-frame consists of 32 bits of information. Each data bit received is coded using a bi-phase mark encoding as a two
binary state symbol. The preambles violate bi-phase encoding so they may be differentiated from data. In bi-phase
encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. For a logic
0, the second state of the symbol is the same as the first state. For a 1, the second state is the opposite of the first. Figure
7 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2
Frame 191
Sub-frame Sub-frame
Frame 0
Frame 1
Figure 6. Block format
0110 0010
Figure 7. A biphase-encoded bit stream
MS0014-E-01
- 17 -
2000/07