AKD7780 Datasheet, PDF (30/48 Pages) Asahi Kasei Microsystems – 24-bit stereo ADC’s, a mono ADC and a stereo SRC.

5
4
3
JP1
+ C1
AVDD_SRC
100uF(A)
1
2
3
4
5
6
AINM
7
8
AINR4
9
10
AINL4
11 12
AINR3
13 14
AINL3
15 16
AINR2
17 18
AINL2
19 20
AINRN
21 22
AINRP
23 24
AINLN
D
25 26
27 28
AINLP
AINR5
29 30
AINL5
31 32
AINR6
33 34
AINL6
35 36
AINR7
37 38
AINL7
39 40
AINR8
41 42
AINL8
43 44
45 46
C9
+ C8
100uF(A)
AVDD_AD ^{47 48}
49 50
HEADER 25X2
AVSS_CHIP
10uF
C10
AVDD_AD
C11
R2
1.5k(DIP)
47nF(DIP)
U1
0.1uF
C
DVDD18_CHIP
+ C13
100uF(A)
DVSS_CHIP
JP5
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
HEADER 15X2
TEST1
I2CSEL
SRCSET1
SRCSET0
MCLK
CKM1
CKM0
CKM2
LRCLK_O
BITCLK_O
SDOUT1
SDOUT2
SDOUT3
SDOUT4
SDOUT5
HEADER 3
1
2
3
default 1-2short JP7
B
AVSS_CHIP
default short
JP3
HEADER 2
1
AVSS_CHIP 2
AVDD_AD
3
4
5
6
7
BVSS1
8
DVDD_CHIP 9
DVSS_CHIP 10
XTI
11
XTO
12
DVSS_CHIP 13
DVDD18_CHIP 14
15
16
17
DVDD18_CHIP 18
DVSS_CHIP 19
DVDD_CHIP 20
21
R7
100
22
R9
100
23
R11
100
24
R12
100
25
LFLT
AVSS1
AVDD1
TEST1
I2CSEL
SRCSET1
SRCSET0
BVSS1
DVDD1
DVSS1
XTI
XTO
DVSS2
DVDD18_2
CKM1
CKM0
CKM2
DVDD18_3
DVSS3
DVDD3
LRCLK_O
BITCLK_O
SDOUT1
SDOUT2
SDOUT3
AK7780
C19
22pF(DIP)
R13
0(DIP)
X'TAL1
12.288MHz
C20
22pF(DIP)
R14
100
R15
100
TP(BLACK)
TP2
+ C31
100uF(A)
DVDD_CHIP
DVSS_CHIP
JP9
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
HEADER 15X2
R16
100
SDIN2
SDIN3
SDIN4
SDIN5
BITCLK_I
LRCLK_I
INIT_RESET
P_CKRST
P_ADRST
P_DSPRST
RQ_N
SI
SCLK
SO
CLKO1
HEADER 2
1
2
JP8
R17
0(DIP)
R18
0(DIP)
R21
0(DIP)
R19
0(DIP)
R20
0(DIP)
A
C44
C45
C46
C47
C48
0uF(DIP)
0uF(DIP)
0uF(DIP)
0uF(DIP)
0uF(DIP)
2
1
AVDD_AD
AVDD_SRC
C2
+ C3
C4
+ C5
C6
+ C7
0.1uF
10uF
0.1uF
10uF
0.1uF
10uF
D
TP(BLUE)
TP1
SRC_LFLT ⁷⁵
AVSS2 ⁷⁴
AVDD2 ⁷³
TEST2 ⁷²
P_SRCSMUTE ⁷¹
BVSS2 ⁷⁰
DVDD_8 ⁶⁹
DVSS_8 ⁶⁸
DVDD18_8 ⁶⁷
P_SRCRST ⁶⁶
SDA ⁶⁵
SRC_LRCK ⁶⁴
SRC_BICK ⁶³
SDIN1 ⁶²
JX0 ⁶¹
JX1 ⁶⁰
JX2 ⁵⁹
DVDD18_7 ⁵⁸
DVSS_7 ⁵⁷
DVDD_7 ⁵⁶
CLKO2 ⁵⁵
SDOUT6 ⁵⁴
SDOUTA1 ⁵³
STO ⁵²
RDY ⁵¹
R1
1.5k(DIP)
C12
1.5uF(DIP)
C14
8.2nF(DIP)
JP4
HEADER 2
AVSS_CHIP
AVDD_SRC
default short
BVSS2
DVDD_CHIP
DVSS_CHIP
DVDD18_CHIP
R4
0(DIP)
R5
0(DIP)
R6
0(DIP)
AVSS_CHIP
DVDD18_CHIP
DVSS_CHIP
DVDD_CHIP
R8
100
R10
100
TEST2
P_SRC_SMUTE
P_SRC_RST
SDA
SRC_LRCK
SRC_BICK
SDIN1
JX0
JX1
JX2
R3
100
JP6
HEADER 2
CLKO2
SDOUT6
SDOUTA1
STO
RDY
AK7780
C16
0uF(DIP)
C17
0uF(DIP)
C18
0uF(DIP)
JP2
30 29
28 27
26 25
24 23
22 21
20 19
18 17
16 15
14 13
12 11
10
9
8
7
6
5
4
3
2
1
HEADER 15X2
DVDD18_CHIP
DVSS_CHIP
C
+ C15
100uF(A)
B
DVDD_CHIP
C21
0.1uF
+ C27
10uF
C22
0.1uF
+ C28
10uF
C29
0.1uF
+ C23
10uF
C24
0.1uF
+ C25
10uF
C30
0.1uF
C26
0.1uF
(9,10) (9,10) (19,20) (19,20) (29,30) (29,30) (48,49) (56,57) (56,57) (68,69)
DVDD18_CHIP
C32
0.1uF
+ C33
10uF
C34
0.1uF
+ C35
10uF
C36
0.1uF
C37
0.1uF
+ C38
10uF
C39
0.1uF
+ C40
10uF
C41
0.1uF
C42
0.1uF
+ C43
10uF
(13,14) (13,14) (18,19) (18,19) (30,31) (38,39) (38,39) (47,48) (47,48) (57,58) (67,68) (67,68)
A
Title
Socket
Size
A2
Document Number
<Doc>
Rev
NC
Date:
Wednesday, July 12, 2006
Sheet
1
of 1
5
4
3
2
1