AKD4364 Datasheet, PDF (3/30 Pages) Asahi Kasei Microsystems – EVALUATION BOARD REV.A FOR AK4364

ASAHI KASEI
[AKD4364]
2) Ideal sine wave generated by ROM data
Digital signals generated by AKD43XX are used. PORT3 (ADC/ROM) is used to interface with AK43XX.
Master clock is sent from AKD4364 to AKD43XX and LRCK, BICK, SDTI are supplied from AKD43XX to
AKD4364. In case of using external clock through a BNC connector (J4), select “BNC” on JP14 (CLK) and
short JP15 (XTE).
JP6
JP7
JP12
JP13
JP14
JP15
LRCK
BICK
DIR_DATA DIR
CLK
XTE
DIR
ADC
DIR
ADC
VD
GND
DIR
BNC
XTL
3) DIR(CS8414)
PORT4 (TORX174) is used for the evaluation using such as test disk. The DIR generates MCKI, BICK,
LRCK, SDTI from the received data through optical connector. In this case, the EXT bit of AK4364 should be
“1” (External clock mode). Select “RCA” or “OPT” on JP16 (RCA/OPT) in case of using RCA connector (J3)
or optical connector (PORT4: TORX174).
JP6
JP7
JP12
JP13
JP14
JP15
LRCK
BICK
DIR_DATA DIR
CLK
XTE
DIR
ADC
DIR
ADC
VD
GND
DIR
BNC
XTL
n Clock (MCLK,BICK,LRCK) set up
In case of using evaluation mode 1), JP9,10 and 17 should be set up as follows.
They need no care for other evaluation mode.
MCLK
128fs
256fs
512fs
1024fs
JP9
(X_MCLK)
x1
x1
x2
x4
JP10
BICK
(X_LRCK)
x1/128
32fs
64fs
128fs
x1/256
32fs
64fs
128fs
x1/256
32fs
64fs
128fs
x1/256
32fs
64fs
128fs
Table 1. Clock set up
JP17
(X_BICK)
x1/4
x1/2
x1
x1/8
x1/4
x1/2
x1/8
x1/4
x1/2
x1/8
x1/4
x1/2
default
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