AKD4356 Datasheet, PDF (3/27 Pages) Asahi Kasei Microsystems – EVALUATION BOARD REV.B FOR AK4356

ASAHI KASEI
[AKD4356]
n Operation sequence
1) Set up the power supply lines.
[AVDD] (orange) = 4.5∼5.25V
[DVDD] (orange) = 4.5∼5.25V
[VD] (red) = 3.4∼5.0V
[VP+] (green) = +12V∼+15V
[VP-]
(blue) = -12V∼-12V
[AGND] (black) = 0V
[DGND] (black) = 0V
Each supply line should be distributed from the power supply unit.
2) Set-up the evaluation modes, jumper pins and DIP switches (See the followings.)
3) Power on.
The AK4356 should be reset once bringing SW1(-PD) “L” upon power-up.
n Evaluation mode
Applicable evaluation modes
1) DIR (Optical Link and RCA) (default)
2) Using ROM data (AK43XX)
3) Using AKM’s evaluation board for ADC
4) Feeding all signals from external
1) DIR (Optical Link and RCA) <default>
PORT4(TORX174) or J1(RCA) is used. All clock are supplied from CS8414(DIR). DIR generates MCLK,
BICK, LRCK and SDATA from the received data through optical connector (TORX174) or RCA connector.
Used for the evaluation using CD test disk. Nothing should be connected to PORT2,3. In case of using optical
connector (TORX174), select “OPT” on JP17(RCA/OPT). In case of using RCA connector, select “RCA”.
JP4
LRCK
JP7
BICK
JP15
XTI
JP16
XTE
JP14
DIR
JP13
SDATA
ADC DIR ADC DIR
VD GND
2) Ideal sine wave generated by ROM data
Connect the AKD43XX with PORT3(AD/ROM). AKD4356 sends MCLK to AKD43XX, and receives LRCK,
BICK and SDATA. In case of using external master clock through a BNC connector, select “BNC” on JP15(XTI)
and short JP16(XTE).
JP4
LRCK
JP7
BICK
JP15
XTI
JP16
XTE
JP14
DIR
JP13
SDATA
ADC DIR ADC DIR
VD GND
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