AK4340_06 Datasheet, PDF (3/23 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

ASAHI KASEI
[AK4340]
PIN / FUNCTION
No. Pin Name
I/O Function
1 MCLK
I
Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK
I Audio Serial Data Clock Pin
3 SDTI
I Audio Serial Data Input Pin
4 LRCK
I L/R Clock Pin
Power-Down Mode Pin
5 PDN
I
When at “L”, the AK4340 is in the power-down mode and is held in reset.
The AK4340 must be reset once upon power-up.
6 ^SMUTE
I
Soft Mute Pin in parallel control mode
“H”: Enable, “L”: Disable
CSN
I Chip Select Pin in serial control mode
7 ^ACKS
I
Auto Setting Mode Pin in parallel control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CCLK
I Control Data Clock Pin in serial control mode
8
DIF0
CDTI
I Audio Data Interface Format Pin in parallel control mode
I
Control Data Input Pin in serial control mode
9 AOUTR
O Rch Analog Output Pin
10 AOUTL
O Lch Analog Output Pin
11 HVEE
Output Buffer Negative Power Supply Pin
-
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
12 VSS
- Ground Pin
13 VDD
- DAC Power Supply Pin
14 P/S
I
Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
15 NC
-
No connect
No internal banding
(Note)
16 GAIN
I
Output Gain Select Pin
“L”: 0dB, “H”: +1.94dB
Note: Do not allow digital input pins except pull-up pin to float.
Note: Pin No.15 (NC) has no internal bonding and can be left Open, connected GND or VDD.
MS0501-E-00
-3-
2006/04