AK1573 Datasheet, PDF (28/42 Pages) Asahi Kasei Microsystems – Low Noise Integrated VCO

[AK1573/AK1573B/AK1573C]
13. Function Descriptions
13.1. Lock detect
Lock detect output can be selected by LD bit in <Address0x04>. When LD bit = “1”, LD pin outputs a
phase comparison result which is from phase detector directly (This is called “analog lock detect”).
When LD bit = “0”, the output is the lock detect signal according to the on-chip logic (This is called
“digital lock detect”).
The digital lock detect can be done as following :
The LD pin is in unlocked state (which outputs “L”) when a frequency setup is made.
In the digital lock detect, the LD pin outputs “H” (which means the locked state) when a phase error
smaller than a cycle of [REFIN] clock (T) is detected for N times consecutively. When a phase error
larger than T is detected for N times consecutively while the LD pin outputs “H”, then the LD pin
outputs “L” (which means the unlocked state). The counter value N can be set by LDCNTSEL bit in
<Address0x04>. The N is different between “unlocked to locked” and “locked to unlocked”.
LDCNTSEL bit
0
1
unlocked to locked
N=15
N=31
locked to unlocked
N=3
N=7
The lock detect signal is shown below
Reference clock
Phase Comparison signal
T/2
Divided VCO signal
Phase detector output signal
This is ignored because it
cannot be sampled.
LD pin output
Valid ignore
ignore Valid
d
Case of R counter = 1 (Note)
ignore
The LD pin outputs HIGH when a
phase error which is smaller than T/2
is detected for N times consecutively.
Reference clock
Phase Comparison signal
T
Divided signal of RF signal
PFD output signal
This is ignored because it
cannot be sampled.
LD pin output
Valid ^{This is ignored}
because it cannot
be sampled.
Valid
Case of R counter > 1 (Note)
ignore
The LD pin outputs will be HIGH
when a phase error which is smaller
than T is detected for N times
consecutively.
* R counter can be set by R[13:0] bits in Address0x03
Figure.26 Digital Lock Detect Operations
015009351-E-00
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